San Diego, California, US / Engineering / Full Time
Sr. Staff / Principal ASIC Design Engineer
The Senior Staff, Principal ASIC Design Engineer is responsible for designing ASIC and FPGA used in Nextivity Cel-Fi products. Be a team player and works with other engineering teams (software, hardware and system) on architecture and system validation. Responsible for ASIC and FPGA design, verification, prototyping and qualification.
Essential Duties & Responsibilities
- Architecture, design, verification and validation for Cel-Fi products’ ASIC and FPGA
- Support other teams during the development of Cel-Fi products
- Be proactive and identify problems early
- Deliver on schedule
Will be using the tools below:
- System Verilog
- Perl, awk or sed scripting
- GIT version control system
- Cadence simulator, linter and code coverage
- Xilinx & Intel FPGA tools
Skills & Abilities
- Extensive experience in designing cellular modems such as WCDMA, LTE or 5G
- Extensive experience in designing signal processing blocks such as filters or FFT
- Nice to have High speed transceivers interfaces such as CPRI or JESD204B
- Basic knowledge of C language, for the purpose of writing test code for ASIC and FPGA validation
- Good scripting capability with Perl, Awk, sed etc…
- Time management and capability to ensure that business goals are timely met
- Must be proactive, taking initiative and working in a collaborative team environment
- Must demonstrate excellent problem-solving and decision-making skills.
- Ability to work in a fast-paced environment
- Excellent verbal and written communication skills
- Foster a professional attitude and demonstrate integrity and flexibility
- Entrepreneurial, rapid learner, inquisitive, and persistent
- Excellent organizational skills and attention to detail
- Ability to efficiently use video conferencing tools to manage interactive meetings and webinars as needed
- Ability to travel as needed
- Minimum Bachelor’s, Engineering, or other similar degree
- Preferred Master’s degree in Science, Engineering, or related field
- Minimum of 10 to 15 years of ASIC & FPGA design.
- Proven successful experience completing multiple ASIC tape-out, preferably as a technical chip leader.
- Proven successful experience completing multiple FPGA designs for ASIC prototyping and products.
- Experience working with other teams (software, hardware, and system).